Integrated chips are formed by complex fabrication processes comprising a plurality of steps including film depositions, dopings, thermal anneals, etc. These complex processes can be used to form integrated chips having a plurality of diverse devices (e.g., analog devices, digital devices, etc.). For example, single integrated chips having broad functionality (e.g., digital, analog, mixed-signal, and radio-frequency functions) that may extend into the radio frequency and mixed-signal areas require the integration of passive devices, such as capacitors and/or resistors, on to an IC die. Many devices have operational characteristics that are heavily dependent upon their spatial layout. Therefore, during the formation of such devices variations in the fabrication process (process variations) can have a large impact on the operational characteristics of such devices by changing the spatial layout of the devices.
For example, there are various types of capacitors that can be used on integrated chips. Metal-oxide-silicon (MOS) capacitors can be used as a passive capacitor. Metal-insulator-metal capacitors (MIM or MIM cap) are also commonly found in integrated chips. As the name implies, MIM caps are usually found between interconnect metal levels. MIM caps are integrated into various integrated circuits for applications such as analog-logic, analog-to-digital, mixed signal and radio frequency circuits. Current methods of integration of MIMs into integrated circuits require multiple photolithographic and etching steps.
FIG. 1 illustrates a cross sectional view of a typical MIM capacitor. Although FIG. 1 illustrates a MIM cap, it will be appreciated that other capacitors (e.g., MOS caps) share a similar structure. As shown in FIG. 1, a MIM cap 100 is formed over a semiconductor body 102. The MIM cap 100 is configured to comprise a lower gate electrode layer 104 (e.g., M3) comprised within dielectric material 106 and an upper gate electrode layer 110 (e.g., M4) comprised within dielectric material 112. As shown in FIG. 1, the lower gate electrode 104 is vertically separated from the upper gate electrode layer 110 by one or more dielectric layers 108. Typically the one or more dielectric layers 108 are comprised of high k dielectric material to increase capacitance of the device 100 while decreasing the size. Precision capacitors often use one or more dielectric layers comprising an oxide-nitride-oxide (ONO) dielectric stack, which allows for thinner layers and increased performance. Alternatively, other materials such as tantalum oxide (Ta2O5) or hafnium oxide (HfO2) are also used. It will be appreciated that capacitors may also comprise additional layers between the lower and upper metal plates also.
Accordingly, as shown in FIG. 1, precise process control of film deposition thickness of a dielectric layer in a capacitor is important to the performance of the device. Other devices share a similar dependence between performance and process control of thin film depositions. For example, standard analog and mixed signal silicon processes require precise control of the thickness of deposited films/layers to provide uniformity of the design from fab-to-fab, lot-to-lot, wafer-to-wafer, and even within a wafer.
Various techniques are often used to provide uniformity of deposited films. For example, standard techniques comprise providing multiple sources for the deposition of gases, providing uniformity of temperature across a semiconductor wafer, providing uniformity of plasma conditions across the wafer. None the less, such techniques still allow for variation within the devices and often it is necessary to implement a method of making a post fabrication adjustment to the devices to bring device specifications back within their original design value.